The semiconductor devices in integrated circuits (ICs) are well-known to be particularly susceptible to damage by electrostatic discharge (ESD). This is particularly true for metal oxide semiconductor field effect transistors (MOSFETs), but is also a problem for small geometry bipolar devices. Susceptibility to ESD is principally due to the fact that the devices inside an IC are formed from small regions of P-type and N-type semiconducting materials and thin insulating oxides. When an accumulation of static charge is suddenly applied to a device, a normally reverse-biased PN junction may be activated into a regime of high current. If the ESD voltage is sufficiently high, permanent damage to the junctions, surrounding oxides, and/or interconnect metal may result.
An integrated circuit typically experiences an ESD event via the application of static charge to one of its input or output (I/O) terminals (or "pads"). To prevent an excessive static charge from reaching the operating circuits inside the chip, an extra semiconductor device, called an ESD clamp device, is connected between the operating circuits and each pad. The ESD clamp should not affect normal operation of the IC. However, during an ESD event, the ESD clamp shunts the resulting high currents away from the operating circuits, and clamps the pad to a hold voltage known to be safe.
There are two arrangements commonly used for ESD protection, the so-called grounded-gate clamp and the diode-connected clamp. In the grounded arrangement, the ESD transistor is connected between the pad and a ground reference. The control terminal of the transistor is grounded as well. For example, if an N-channel MOSFET is used as the ESD clamp, its drain terminal is connected to the pad, and its source and gate terminals are connected to ground. The ESD clamp thus remains off in normal operation, and its presence does not affect the operating logic circuits.
However, during an ESD event, the pad voltage increases, and a trigger voltage is eventually reached which permits current to begin to flow from the pad through the channel to ground. The ESD clamp then eventually settles into a fairly stable, bipolar conduction region, where it remains clamped at a hold voltage, Vhold, over a wide range of pad currents.
A grounded ESD clamp has certain shortcomings, however. Semiconductor devices are normally made as small as possible, so that as many as possible will fit within a single IC. The trigger voltage of the ESD clamp should normally be as high as possible, to prevent premature triggering. However, guaranteeing a high trigger voltage is difficult with small geometry devices.
Furthermore, although a grounded-gate MOSFET clamp will remain off during normal operation of the IC, full range swing switching voltages will appear at its drain terminal via the pad. The resulting continuous abnormal stress on the drain to gate oxide of the MOSFET clamp may actually change its operating characteristics over the long term.
A diode-connected clamp overcomes certain of these difficulties. It consists of an ESD device having its control terminal connected to the pad instead of ground. The threshold, or "turn-on" voltage, Vt, of the ESD device is tailored, so that it remains off in normal operation of the IC. During an ESD event, however, when the pad voltage rises above Vt, the ESD clamp is enabled to shunt the voltages and currents appearing at the pad to ground.
The channel current induced in a diode-connected clamp helps avoid the need for high trigger voltages or continuous stress on the drain to gate interface. Unfortunately, diode-connected clamps have certain other problems. While drain to gate stress is avoided, source to gate stress is created.
The Vt of the ESD clamp must normally be increased, to insure that it remains off during normal, non-ESD operation. However, the higher Vt also means that a higher clamping voltage results. It is, however, typically advantageous to clamp to as low a voltage as possible during an ESD event, so that the protected logic circuits see as small a voltage as possible.
Another problem with ESD clamps of both types occurs because of parasitic capacitance effect. This effect may enable an output transistor in the operating circuits during the early stages of an ESD event. If this activated output transistor then reaches its trigger voltage before the diode-connected ESD clamp reaches its own trigger voltage, the operating circuits will be exposed to ESD damage.
In addition, the supply voltage used for the operating circuits internal to the chip are sometimes lower than the maximum signal voltages applied to the pads. While this permits the operating circuits internal to the IC to consume less power, it also exacerbates the design of the ESD clamp. For example, an ESD clamp may be required to permit a five-volt signal to pass through the pad to the operating circuits, while still adequately protecting two-to-three volt internal operating devices.
What is needed is an ESD protection circuit which provides the advantages of a grounded clamp, by remaining off during normal operation, and the advantages of a diode-connected clamp, by quickly reaching a hold voltage during an ESD event.
The protection circuit should remain completely off during normal operation of the IC, even in the presence of signal voltages at the pad which exceed the threshold voltage of a standard transistor. The protection circuit should also be quickly placed in the hold state upon the occurrence of an ESD event, without the need for a high trigger voltage to occur first.